The invention relates to a current mode device, in the sequel also denoted as CMD, being supplied via a first supply terminal and a second supply terminal, in the sequel also denoted as CMD, comprising
a first pair of voltage controlled current sources (CCS) being supplied by a first current source adapted to supplying a first current, the first pair of CCS having a first input, a second input, a first output and a second output, first input being coupled to a first input terminal adapted to transmit a first input signal and the second input being coupled to a second input terminal adapted to transmit a second input signal,
the CMD further comprises a second pair of CCS being supplied by a second current source adapted to supplying a second current, the second pair of CCS having a third input, a fourth input, a third output and a fourth output, the third input being coupled with the first output and the fourth input being coupled with the second output for generating a first logical output signal at the third output and a second logical output signal at the fourth output depending on the first input signal and on the second input signal, respectively,
the CMD further comprises an active load circuit being coupled to the first pair of CCS via the first output and via the second output.
The invention further relates to a communication arrangement comprising the current mode circuit.
Current mode devices (CMD) are widely used in high speed digital circuits being well known as emitter-coupled logic (ECL) circuits when they are realized in bipolar technology or as source-coupled logic (SCL) circuits when they are realized in CMOS technology. The basic CMD is the inverter/buffer that is used as an input and/or output device in order to provide sharp edges for a digital signal.
For such an inverter/buffer it is desirable to be able to work at it""s input with digital signals with relatively slow edges and to provide at it""s output digital signals with sharp edges and sufficient energy to be transmitted unaltered in relatively large digital networks.
Digital signal edges deteriorate when the respective signals are transmitted on relatively long transmission lines, when, because of parasitic elements of the transmission line (e.g. parasitic capacitance) the signal is integrated. It should be pointed out here that when relatively high frequency signals are involved, a connection within a chip could be considered to be a relatively long transmission line. A digital network of any kind (optical, electrical, radio-electrical) could be considered to be a long transmission line, too.
A current mode device as described in the opening paragraph is disclosed in U.S. Pat. No. 5,798,658. It comprises a SCL circuit having a differential pair of CMOS transistors being supplied by a current source. The differential pair of CMOS transistors has a load in each of their drains realized with CMOS transistors used as active resistors, the value of their resistance being controlled by a voltage generated by a bias circuit. The drains of the SCL circuit are further coupled to output CMOS transistors connected as source followers, an output signal being obtained in the sources of the output transistors. Furthermore, in the sources of the output transistors, pull down CMOS transistors that are also controlled by the bias circuit are provided, too. It should be pointed out here that because of the source follower transistors the power gain of the circuit is relatively low.
It is therefore an object of the present invention to providing a current mode device having an improved power gain.
In accordance with the invention, this object is achieved in a device as described in the introductory paragraph, which is characterized in that the current mode device further comprises a third pair of CCS being supplied by a third current source adapted to supplying a third current the third pair of CCS having a fifth input and a sixth input coupled to the first input terminal and to the second input terminal, respectively, for providing a fifth output signal at a fifth output and a sixth output signal at a sixth output for controlling an amplification of the first input signal and the second input signal through the first pair of CCS.
The device according to the invention has the advantage of a better power gain at a relatively high frequency of operation providing at its outputs digital signals that have relatively sharp edges. The ratio between the third current C3 and the first current C1 controls the switching speed of the first pair of CCS improving the edges of the signals passing through it. The ratio between the first current C1 and the second current C2 controls the overall delay of the circuit. Because the edges of the input signal are made relatively sharp in the first pair of CCS, the second pair of CCS can be arrange to provide an improved power gain in comparison with the prior art (e.g. common emitter pair instead of common drain pair).
In an embodiment of the invention the active load of the first differential pair of CCS is controlled by the fifth output O3 and the sixth output O3n. The current C3 determines a static supplying current in the active load. The input signals I and In modulate this static supplying current. This has the effect that the active load impedance is dependent on the instant value of the input signals.
In a preferred embodiment of the invention the signal at the first output O1 and the signal at the fifth output O3 are substantially in phase, and the signal at the second output O1n and the signal at the sixth output O3n, are substantially in phase, too. If the phase of the input signal I slightly differs from the phase of the input signal In, then this difference is controllably amplified by the first pair of CCS, shortening the input signal delay through the device, the overall delay being dependent on a ratio between the currents C1 and C3. The signals obtained at the first output O1 and the second output O1n drive the third input I2 and the fourth input I2n, respectively. The second pair of CCS, supplied by the second current C2, have a relatively high power gain, the overall power gain of the device being relatively high. Furthermore, because of the relatively high power gain, the edges of the first output signal O and the second output signal On are relatively sharp. It should be pointed out here that the overall delay through the device is further dependent on a ratio between the second current C2 and the first current C1.
It is another object of the present invention to provide a communication arrangement comprising an emission module coupled with a reception module via a bi-directional communication channel, further comprising in the emission module and in the reception module the current mode circuit as claimed in claim 1. It should be pointed out here that if the communication channel is a long line (a computer network, e.g.) the edges of the digital signals circulating through it deteriorate especially because of the parasitic impedance (capacitors, inductors, e.g.) of the channel. Furthermore, if a very high frequency chip is considered, the connection lines within the chip behave as a transmission line deteriorating the edges of the digital signals. It is therefore necessary for the emission module to have a current mode circuit for providing digital signals with sharp edges and, in the same time, the reception module must have a current mode circuit for supplying reliable digital signals to the other circuits of the reception module.